The inventive concepts described herein relate to semiconductor devices, and more particularly to a method of powering-off semiconductor devices.
In system-on-chips (SoCs), dozens of power sources may be supplied from a power management integrated chip (PMIC) typically having complicated power supply configuration. The dozens of power sources are individually controlled over units of micro-seconds or units of a given time when powered-on.
The reason for controlling the power sources at such a fine level when powered-on is to prevent inrush current and to stably supply power to individual power sources.
However, it is difficult to control the power sources at fine levels during a power-off operation. Since voltage levels of the power sources decrease due to discharge when powered-off, the amount of time to completely power-off the power sources may be delayed differently by an amount of charge charged in capacitors of the power sources, a magnitude of a resistance to be discharged, a magnitude of an external capacitance, or the like.
If power-off control is performed following all the sequences as in a power-on operation, the power-off time may become slower than the power-on time by dozens to several hundred times. This may cause issues such as poor responsiveness or poor reaction speed.